The present invention relates to a variable-capacitance device, and more particularly, to a variable-capacitance device whose capacitance is switched by switching the number of capacitors coupled in parallel.
A circuit formed in a semiconductor device may include a capacitance element. However, in such a semiconductor device, it is difficult to change the capacitance of the capacitance element after production of a semiconductor chip is complete. To solve the problem described above, it is known to use a variable-capacitance device whose capacitance can be changed after the production of the semiconductor chip is complete. The variable-capacitance device is an element whose capacitance can be switched or changed, for example, in accordance with a control signal. Examples of variable-capacitance devices may be found, for example, in U.S. Pat. No. 5,594,388, and Japanese Patent Laid-Open No. 2008-252774.
FIG. 17 illustrates a circuit diagram of a variable-capacitance device 100 equivalent to a variable-capacitance device disclosed in U.S. Pat. No. 5,594,388. As shown in FIG. 17, the variable-capacitance device 100 includes capacitors C1 and C2 and a capacitance selection switch 101. The variable-capacitance device 100 also includes an output terminal COUT at one end of the variable-capacitance device 100. The other end of the variable-capacitance device 100 is supplied with a ground voltage VSS.
The capacitor C1 is coupled between the output terminal COUT and a ground terminal to which the ground voltage VSS is supplied. The capacitor C2 is provided such that the capacitor C2 is coupled in parallel to the capacitor C1 and coupled in series to the capacitance selection switch 101. More specifically, one end of the capacitor C2 is coupled to the ground terminal, and the other end is coupled to one terminal of the capacitance selection switch 101. Hereafter, a node at which the capacitance selection switch 101 and the capacitor C2 are coupled is denoted by ND1. The other terminal of the capacitance selection switch 101 is coupled to the output terminal COUT. The capacitance selection switch 101 is configured in the form of a transfer switch. The capacitance selection switch 101 includes an NMOS transistor N101, a PMOS transistor P101, and an inverter INV101. The source of the NMOS transistor N101 and the source of the PMOS transistor P101 are coupled together. The drain of the NMOS transistor N101 and the drain of the PMOS transistor P101 are coupled together. A capacitance switching signal CSEL is input to the gate of the NMOS transistor N101. The capacitance switching signal CSEL is input to the gate of the PMOS transistor P101 via the inverter INV101. The capacitance selection switch 101 is in an ON state when the capacitance switching signal CSEL is in an enable state (more specifically, for example, when it is at a high level), while the capacitance selection switch 101 is in an OFF state when the capacitance switching signal CSEL is in a disable state (more specifically, for example, when it is at a low level).
When the capacitance selection switch 101 is in the ON state, the variable-capacitance device 100 has capacitance equal to the sum of the capacitance of the capacitor C1 and the capacitance of the capacitor C2. On the other hand, when the capacitance selection switch 101 is in the OFF state, the variable-capacitance device 100 has capacitance equal to the capacitance of the capacitor C1.
FIG. 18 is a circuit diagram of a variable-capacitance device 200 equivalent to a variable-capacitance device disclosed in Japanese Patent Laid-Open No. 2008-252774. As shown in FIG. 18, the variable-capacitance device 200 includes capacitors C1 and C2 and a switch circuit (more specifically, an NMOS transistor N201 in the example shown in FIG. 18). The variable-capacitance device 200 has an output terminal COUT at one end of the variable-capacitance device 200. A ground voltage VSS is supplied to the other end of the variable-capacitance device 200.
The capacitor C1 is coupled between the output terminal COUT and a ground terminal to which the ground voltage VSS is supplied. The capacitor C2 is provided such that the capacitor C2 is coupled in parallel to the capacitor C1 and coupled in series to the NMOS transistor N201. The source of the NMOS transistor N201 is coupled to the ground terminal, and the drain of the NMOS transistor N201 is coupled to one end of the capacitor C2. Hereinafter, a node at which the drain of the NMOS transistor N201 and the capacitor C2 are coupled together is denoted by ND2. The other end of the capacitor C2 is coupled to the output terminal COUT. A capacitance switching signal CSEL is input to the gate of the NMOS transistor N201. The NMOS transistor N201 is in an ON state when the capacitance switching signal CSEL is in an enable state (more specifically, for example, when it is at a high level), while NMOS transistor N201 is in an OFF state when the capacitance switching signal CSEL is in a disable state (more specifically, for example, when it is at a low level).
When the NMOS transistor N201 is in the ON state, the variable-capacitance device 200 has capacitance equal to the sum of the capacitance of the capacitor C1 and the capacitance of the capacitor C2. On the other hand, when the NMOS transistor N201 is in the OFF state, variable-capacitance device 200 has capacitance equal to the capacitance of the capacitor C1.